1. Field of the Invention
Embodiments discussed herein are related to a semiconductor device and method of manufacturing a semiconductor device.
2. Description of the Related Art
Insulated gate field effect transistors (Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)) with a voltage class of 400 V, 600 V, 1200 V, 1700 V, 3300 V, 6500 V, or greater are known as power semiconductor devices. For example, a MOSFET using a silicon carbide (SiC) semiconductor (hereinafter referred to as a SiC-MOSFET) is used in power converting equipment such as a converter/inverter. Lower loss and higher efficiency as well as reduced leak current at the time of turning-off, a smaller size (reduction in chip size), and improved reliability is demanded of such power semiconductor devices.
A vertical MOSFET has a built-in parasitic pn diode formed of a p-type base region and an n-type drift layer as a body diode between the source and drain. Therefore, a free-wheeling diode (FWD) used in an inverter may be eliminated, contributing to reductions in cost and size. However, when a silicon carbide substrate is used as a semiconductor substrate, the parasitic pn diode has a higher built-in potential as compared to the case of using a silicon (Si) substrate and therefore, on-resistance of the parasitic pn diode increases, resulting in increased loss. Additionally, characteristics change over time (degradation occurs over time) consequent to bipolar operation of the parasitic pn diode when the parasitic pn diode is turned on and energized and reliability decreases.
In this regard, an example of a conventional trench type SiC-MOSFET including a contact trench (source trench) between adjacent gate trenches will be described (see, for example, Nakano, Y., et al, “690V, 1.00 mΩcm2 4H—SiC Double-Trench MOSFETs”, Materials Science Forum (Switzerland), Trans Tech Publications Inc., Vols. 717-720, pp. 1069-1072, 2012). A gate trench is a trench in which a gate electrode is embedded via a gate insulating film. A contact trench is a trench in which a metal electrode (source electrode) is embedded to form a contact (electric contact portion) between a semiconductor region exposed on an inner wall and the metal electrode. First, a structure of the conventional trench type SiC-MOSFET (hereinafter, referred to as Conventional Example 1) will be described. FIG. 25 is a cross-sectional view of a structure of an active region of the conventional trench type SiC-MOSFET.
As depicted in FIG. 25, Conventional Example 1 includes a trench type MOS gate (an insulated gate formed of metal-oxide-semiconductor) structure and a contact trench 108 on a front surface of an n-type semiconductor substrate 110 in the active region. The active region is a region having a role in current driving. For example, the n-type semiconductor substrate 110 is formed by epitaxially growing an n−-type layer forming an n−-type drift layer 102 on a silicon carbide substrate that is an n+-type drain layer 101. On a front surface (a surface on the n−-type drift layer 102 side) of the n-type semiconductor substrate 110, a MOS gate structure made up of a p-type base region 103, an n+-type source region 104, a gate trench 105, a gate insulating film 106, and a gate electrode 107 is provided.
To relax an electric field applied to the gate insulating film 106 at a bottom portion of the gate trench 105, the depth of the p-type base region 103 between the adjacent gate trenches 105 (in a mesa portion) is made at least partially deeper than the depth of the gate trenches 105. To make the depth of the p-type base region 103 deeper than the depth of the gate trenches 105, in the mesa portion the contact trench 108 deeper than the depth of the gate trenches 105 is disposed. The p-type base region 103 is disposed to cover a source electrode 111 described later over an entire surface of an inner wall of the contact trench 108 and protrudes deeper than the gate trenches 105 toward the drain. The p-type base region 103 is exposed at the inner wall of the contact trench 108.
The n+-type source region 104 is selectively disposed in the p-type base region 103 between each of the adjacent gate trenches 105 and the contact trench 108. The n+-type source region 104 and the p-type base region 103 exposed at the inner wall of the contact trench 108 are exposed at a contact hole 109a penetrating an interlayer insulation film 109 in a depth direction. The source electrode 111 is disposed as a front surface electrode and embedded in the contact hole 109a and the contact trench 108 and contacts the p-type base region 103 and the n+-type source region 104. A drain electrode (not depicted) is disposed as a back surface electrode on a back surface (a surface on the n+-type drain layer 101 side) of the n-type semiconductor substrate 110.
When a positive voltage is applied to the source electrode 111 and a negative voltage is applied to the drain electrode (at turning off of the MOSFET), a pn junction between the p-type base region 103 and the n−-type drift layer 102 is forward-biased. In Conventional Example 1, when a parasitic pn diode formed of the p-type base region 103 and the n−-type drift layer 102 is turned on and energized at the time of turning off the MOSFET, a bipolar operation of the parasitic pn diode causes degradation over time. When the parasitic pn diode is used as a free-wheeling diode, the utilization of the silicon carbide substrate increases the on-resistance. This problem is eliminated by having a parasitic Schottky diode built-in as a body diode between source and drain (see, for example, Japanese Laid-Open Patent Publication No. 2011-134910).
Since the silicon carbide semiconductor has a higher breakdown electric field intensity to avalanche breakdown as compared to a silicon semiconductor, the parasitic Schottky diode may be used as the body diode even at a high breakdown voltage class of 600 V or more. For example, the parasitic Schottky diode is disposed in parallel with the parasitic pn diode between source and drain so that the parasitic Schottky diode is designed to be turned on before the parasitic pn diode is turned on at the time of turning off the MOSFET. This enables prevention of the degradation caused by the bipolar operation of the parasitic pn diode. Since the parasitic Schottky diode has no built-in potential of the pn junction, a lower on-resistance is expected as compared to when only the parasitic pn diode is formed as the body diode.
A structure of a conventional trench type SiC-MOSFET having a parasitic Schottky diode built-in between source and drain (hereinafter referred to as Conventional Example 2) will be described. FIG. 26 is a cross-sectional view of a structure of an active region of another example of the conventional trench type SiC-MOSFET. Conventional Example 2 is different from Conventional Example 1 (see FIG. 25) in that a parasitic Schottky diode is formed as a body diode at a bottom portion of the contact trench 108. For example, as depicted in FIG. 26, in Conventional Example 2, the depth of a p-type base region 113 is shallower than the depth of contact trench 108, and the contact trench 108 penetrates the p-type base region 113 to the n−-type drift layer 102 in the depth direction.
A metal film 112 made of nickel is disposed along the inner wall of the contact trench 108 and the source electrode 111 is embedded in the contact trench 108, on the metal film 112. The metal film 112 contacts the n−-type drift layer 102 at the bottom portion of the contact trench 108 to form a Schottky junction with the n−-type drift layer 102. The metal film 112 functions as a front surface electrode along with the source electrode 111. The source electrode 111 is electrically connected via the metal film 112 to the n−-type drift layer 102 at the bottom portion of the contact trench 108. As a result, the parasitic Schottky diode is formed of the n−-type drift layer 102 and the front surface electrode (the source electrode 111 and the metal film 112) at the bottom portion of the contact trench 108.
As another trench type MOSFET having a parasitic Schottky diode built-in, a device has been proposed that has a p-type single crystal region of silicon carbide formed in an n-type drift layer in a region facing a curved area of an outer shape of a Schottky electrode formed inside a trench (see, for example, Japanese Laid-Open Patent Publication No. 2013-243207). In Japanese Laid-Open Patent Publication No. 2013-243207, the p-type single crystal region relaxes electric field concentration and suppresses the occurrence of avalanche breakdown to improve the breakdown voltage.
As another trench type MOSFET having a parasitic Schottky diode built-in, a device has been proposed that has respective MOSFET functions implemented at both side walls of a trench as well as a Schottky diode function implemented at a bottom portion of the trench (see, for example, Japanese Patent No. 4874516). In Japanese Patent No. 4874516, a chip area is optimized by incorporating the trench type MOSFET at the side wall of the contact trench having the Schottky diode.
As another trench type MOSFET having a parasitic Schottky diode built-in, a device has been proposed that includes a p-type region at a bottom portion of a contact trench provided with a Schottky diode (see, for example, Japanese Laid-Open Patent Publication No. 2009-278067). In Japanese Laid-Open Patent Publication No. 2009-278067, a p-type region for electric field relaxation is formed at a bottom portion of a contact trench having the Schottky diode so as to improve the breakdown electric field intensity against avalanche breakdown.
As a trench type MOSFET including a p-type region in a trench bottom portion, a device has been proposed that has a deep p-type layer formed to surround a bottom portion and both corners of a gate trench (see, for example, Japanese Laid-Open Patent Publication No. 2008-235546). In Japanese Laid-Open Patent Publication No. 2008-235546, the electric field concentration is prevented in the both corners of the gate trench and the electric field intensity is suppressed to 1 MV/cm or less so as to prevent destruction of a gate oxide film at the both corners of the gate trench.
As another trench type MOSFET including a p-type region at a trench bottom portion, a device has been proposed that has a p-type floating region formed into a substantially circular shape around a bottom portion of a gate trench inside an n-type drift layer (see, for example, Japanese Laid-Open Patent Publication No. 2006-093457). In Japanese Laid-Open Patent Publication No. 2006-093457, peaks of an electric field are formed at two positions in the vicinity of a pn junction between a p-type base region and an n-type drift layer and in the vicinity of a pn junction between the p-type floating region and an n−-drift layer to achieve a higher breakdown voltage, so that a lower on-resistance is achieved.
As another trench type MOSFET including a p-type region in a trench bottom portion, a device is proposed that has a bottom p-type layer formed at a lower portion of a gate trench such that a shallowest position of a portion located at a corner of the gate trench is located on the lower side (on the drain side) as compared to a shallowest position of a portion located inside the corner (see, for example, Japanese Laid-Open Patent Publication No. 2009-158681). In Japanese Laid-Open Patent Publication No. 2009-158681, an interval is widened between the bottom p-type layer and a depletion layer extending from a p-type base region to an n-type drift layer so as to suppress an increase in on-resistance.
As a method of manufacturing another trench type MOSFET including a p-type region in a trench bottom portion, a method has been proposed that includes forming a p-type layer epitaxially grown in a trench before forming a p-type SiC layer by leaving the p-type layer only at a bottom portion and both leading end portions of the trench through hydrogen etching (see, for example, Japanese Laid-Open Patent Publication No. 2013-258369). In Japanese Laid-Open Patent Publication No. 2013-258369, the p-type SiC layer is formed in the bottom portion of the trench without using tilted ion implantation, so as to suppress leak current due to a defective damage of ion implantation.